NVIDIA is deploying its Vera CPU across the electronic design automation workflows used to design its next-generation processors. Early testing with Cadence and Synopsys showed gains on selected workloads.
The move focuses on a part of chip development that still depends heavily on CPU performance, even as graphics processors and artificial intelligence tools take on more work elsewhere in the design process. Logic simulation, formal verification and parts of digital implementation often rely on fast single-core performance, memory efficiency and overall throughput.
NVIDIA is working with Cadence and Synopsys to optimise key electronic design automation applications for Vera. Initial testing covered Cadence Jasper, a formal verification platform, and Synopsys VCS, a functional verification tool used to simulate and validate chip designs before fabrication.
In those tests, both applications recorded up to 1.5 times higher performance on selected workloads using the same number of cores, according to NVIDIA. The work with both software groups also includes application profiling, software optimisation and system-level tuning aimed at improving engineering productivity across a wider set of workflows.
Design bottleneck
The announcement highlights the continuing importance of conventional processor design in semiconductor engineering. Engineers can spend years validating a chip before it reaches manufacturing, running repeated checks to confirm behaviour, find corner cases and refine the architecture through many iterations.
As a result, delays in verification and implementation can slow the broader pace of chip development. Faster runs can reduce the time needed for individual checks, while greater throughput can let teams test more design options within the same development cycle.
Vera is being rolled out inside NVIDIA's own engineering systems as part of that effort. The processor combines 88 custom Olympus CPU cores with an LPDDR5X memory subsystem and the second generation of NVIDIA's Scalable Coherent Fabric.
Those features are intended for workloads that combine latency-sensitive jobs with large regression testing across compute farms. Such tasks are common in modern electronic design automation, where different verification and implementation stages are linked and delays in one stage can affect the next.
Internal use
NVIDIA's use of Vera in its own design operations also points to a broader strategy of matching computing architectures to specific engineering tasks. In practice, that means using GPUs and AI where they improve algorithms, while relying on CPUs for parts of the workflow that remain tied to serial processing, memory behaviour and verification throughput.
The chip design process starts after engineers define the architecture and microarchitecture of a processor. They then describe much of its behaviour at the register-transfer level, after which simulation, formal verification, regression testing and digital implementation tools are used to move the design toward manufacturable silicon.
Because those stages are interconnected, improvements in one area can have wider effects across a project. If verification workloads finish faster, engineering teams can identify issues earlier and avoid some of the more expensive design changes that can emerge later in development.
Tool partners
Cadence Jasper is designed to find and fix bugs earlier in the design cycle through formal verification methods and machine learning. Synopsys VCS is widely used to simulate and validate complex chip designs before fabrication, making it one of the central tools in pre-silicon verification.
NVIDIA did not disclose the full range of workloads tested or provide broader benchmark data beyond the selected cases cited. It said the current results are early, and work continues with both companies on tuning applications and systems for a wider set of engineering tasks.
The deployment also feeds into NVIDIA's longer-term processor plans. The company intends to build on Vera with a later CPU called Rosa, which will use its Rigel core.
By using its own CPUs in the workflows that help design future CPUs and GPUs, NVIDIA is tightening the link between silicon design, software optimisation and systems engineering. The result is a development model in which each generation of internal hardware informs the next.